AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micron interconnect:
Seprate Channels for Read Data,Read Address,Write Data,Write Address and Write Response Channel.In Burst Transfer Only Start Address is issued .support for unaligned data transfers using byte strobes,issuing of multiple outstanding addresses . Easy addition of Register Slice to provide timing close .
While AHB is single clock edge protocol . First should be Address phase and then data phase should come .It supportSplit and Retry Commands , there can be Serveral Bus Masters .It also support Busrt Transfer however bus requere all the address on address lines .
Seprate Channels for Read Data,Read Address,Write Data,Write Address and Write Response Channel.In Burst Transfer Only Start Address is issued .support for unaligned data transfers using byte strobes,issuing of multiple outstanding addresses . Easy addition of Register Slice to provide timing close .
While AHB is single clock edge protocol . First should be Address phase and then data phase should come .It supportSplit and Retry Commands , there can be Serveral Bus Masters .It also support Busrt Transfer however bus requere all the address on address lines .
